DocumentCode
3134864
Title
Fast thermal simulators for architecture level integrated circuit design
Author
Ziabari, Amirkoushyar ; Ardestani, Ehsan K. ; Renau, Jose ; Shakouri, Ali
Author_Institution
Univ. of California Santa Cruz, Santa Cruz, CA, USA
fYear
2011
fDate
20-24 March 2011
Firstpage
70
Lastpage
75
Abstract
High temperatures and non-uniform temperature distributions have become a serious concern since they limit both performance and reliability of Integrated Circuits (IC). With computer architect´s concern to position microarchitecture blocks in a processor, faster thermal models can be developed at the cost of hiding finer grain details such as circuit or transistor level information. Several methods to quickly estimate the surface temperature profiles of microarchitecture blocks have been investigated in recent years. HotSpot simulator is widely used in computer architecture community. SESCTherm is another architecture level thermal simulator which has shown good performance and modularity in modeling. Recently Power Blurring (PB) method has been developed for both steady-state and transient thermal analysis of standard and 3D chips. While some of these methods are validated against finite element and Green´s function based techniques, there are no detailed comparisons of the accuracy and speed for some common applications. In this paper we present the steady-state and transient temperature distributions calculated by these three architecture level thermal simulators. A detailed comparison taking into account the accuracy and the computation speed is performed. Our results indicate that Power Blurring has the potential to be a promising architecture level thermal simulator for fast calculation of temperature profile from the input power map in a realistic package which, in turn, is a key ingredient for full self-consistent simulations.
Keywords
CMOS integrated circuits; Green´s function methods; VLSI; circuit simulation; computer architecture; finite element analysis; integrated circuit design; integrated circuit reliability; microprocessor chips; temperature distribution; thermal analysis; transient analysis; 3D chips; CMOS VLSI; Green´s function based techniques; HotSpot simulator; Power Blurring method; SESCTherm; architecture level integrated circuit design; architecture level thermal simulator; fast thermal simulators; finite element analysis; input power map; integrated circuit reliability; microarchitecture blocks; nonuniform temperature distributions; steady-state analysis; surface temperature profiles; transient thermal analysis; transistor level information; Computational modeling; Finite element methods; Heat sinks; Integrated circuit modeling; Steady-state; Temperature distribution; Transient analysis; HotSpot; Power Blurring; SESCTherm; architectural level thermal simulator; thermal simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2011 27th Annual IEEE
Conference_Location
San Jose, CA
ISSN
1065-2221
Print_ISBN
978-1-61284-740-5
Type
conf
DOI
10.1109/STHERM.2011.5767180
Filename
5767180
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