DocumentCode :
3134984
Title :
Angle-of-attack investigation of pin-fin arrays in nonuniform heat-removal cavities for interlayer cooled chip stacks
Author :
Brunschwiler, Thomas ; Paredes, S. ; Drechsler, U. ; Michel, Bruno ; Wunderle, B. ; Reichl, Herbert
Author_Institution :
IBM Res. - Zurich, Rüschlikon, Switzerland
fYear :
2011
fDate :
20-24 March 2011
Firstpage :
116
Lastpage :
124
Abstract :
Interlayer cooling removes the heat dissipated by vertically stacked chips in multiple integrated fluid cavities. Its performance scales with the number of dies in the stack and is therefore superior to traditional back-side heat removal. Previous work indicated that pin-fin arrays are ideally suited as through-silicon-via-compatible heat transfer structures. In addition, four-port fluid-delivery and fluid-guiding structures improve the heat-removal performance for the nonuniform power maps of high-performance microprocessor chip stacks. Accordingly, an extension of the porous-media multi-scale modeling approach is presented as an efficient approach for designing nonuniform heat transfer cavities. A tensor description in combination with a look-up table is proposed to physically describe periodic porous media, such as pin-fin arrays, in detail. Conjugate heat and mass transfer sub-domain modeling is performed with periodic boundary conditions to derive the orientation-dependent permeability and angle offset between the pressure gradient and the Darcy velocity direction for pin-fin arrays with a pin diameter of 50 μm and pitch and height of 100 μm. A local permeability minimum at a flow direction of approx. 30° could be identified. At higher velocities, the fluid flow is biased towards the symmetry lines of the pin-fin array. The modeling concept was validated with experimental readings of a nonuniform, double-side-heated single test cavity. The main characteristics of the temperature field with respect to the four-port architecture, the guiding structures, the fluid temperature increase, and the nonuniform power dissipation are predicted correctly. A statistical comparison of power maps with different heat transfer contrast values resulted in a mean accuracy <;6% at a maximal standard deviation of 22.2%. Finally, the potential of the four-port architecture for nonuniform power maps with hot spots in the corners was demonstrated.
Keywords :
cooling; integrated circuit packaging; mass transfer; microprocessor chips; permeability; table lookup; three-dimensional integrated circuits; Darcy velocity direction; angle-of-attack; fluid flow; heat dissipation; heat transfer contrast values; heat transfer structures; hot spots; interlayer cooling; look-up table; mass transfer; microprocessor chip stacks; multiple integrated fluid cavity; nonuniform heat-removal cavity; periodic boundary conditions; permeability; pin-fin arrays; porous-media multiscale modeling; size 100 mum; size 50 mum; through-silicon-via; vertically stacked chips; Cavity resonators; Fluids; Heat transfer; Heating; Permeability; Silicon; Temperature measurement; Angle-of-attack; interlayer cooling; multi-scale modeling; nonuniform heat transfer; pin-fin; porous media;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2011 27th Annual IEEE
Conference_Location :
San Jose, CA
ISSN :
1065-2221
Print_ISBN :
978-1-61284-740-5
Type :
conf
DOI :
10.1109/STHERM.2011.5767188
Filename :
5767188
Link To Document :
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