The impact of isolation pitch scaling on V/sub TH/ fluctuation in DRAM cell transistors due to neighboring drain/source electric field penetration

This paper presents the accelerated inverse narrow channel effect of DRAM cell transistors caused by lateral E-field penetration from drain/source junctions of neighboring cell transistors. This phenomenon strongly increases the threshold voltage fluctuation of cell transistors depending on the junction biases of neighboring cell transistors and will impose physical size and the voltage scaling constraints for the Gigabit level DRAM technology.