Interconnect scaling: signal integrity and performance in future high-speed CMOS designs

The impact of new interconnect materials and various circuit design techniques on both performance and signal integrity in future high-speed CMOS is investigated. Specifically, this work examines the use of copper, low-k dielectrics, repeaters, driver sizing and novel design techniques with respect to crosstalk and delay in the 0.25 to 0.07 /spl mu/m generations. We show crosstalk to be very important in scaled ULSI interconnects and steps such as reduced aspect ratios and asymmetric pitches should be used to ensure signal integrity.