Systems oriented architecture of image processor for automated visual inspection

As a practical architecture of high speed image processor for automated visual inspection systems (AVISs), we present a “Building Block” typed pipeline architecture in older to enable the image processing hardware modules (IPMs) to connect each other in many kinds of forms like building blocks. Next, we propose a simple method of timing control to drive the connected IPMs, using videosync signal and image identification number, which aims to overcome the timing difficulty caused by the delay of each IPM. Moreover, we discuss a double-loop structured architecture which has logically two loops of data bus: one is for usual image processing and another for transmission of look-up table (LUT) data of IPMs. Since the architecture can make those data go through each other´s bus, it can use the processed image data as a LUT data, and also it can process the extracted feature data as equivalently as image data This paper also shows some examples of realized AVISs by an implemented processor based on the proposed architecture