High-performance transistor evaluation for low-cost embedded DRAM

High-speed and low-power logic compatible performance is in high demanded for embedded DRAM (eDRAM) and/or custom DRAM applications. However, it is a challenge to make it cost-effectively using the commercial DRAM process. In this paper, the feasibility of high-performance transistors is demonstrated using the commercial Micron Technology 95 nm DRAM process and design targeted for low-cost eDRAM. Multiple process conditions were optimized in the commercial DRAM process to simultaneously achieve the target performance and minimize DRAM retention time degradation. A dual-EPI process-thin selective EPI growth in the peripheral source/drain and thick selective EPI growth in the DRAM cell array-was experimentally developed to improve DRAM retention time. Parametrically, the dual-EPI process was successful, but further optimization is required for good yield.