Low resistance dual damascene process by new Al reflow using Nb liner

Author

Wada, J. ; Oikawa, Y. ; Katata, T. ; Nakamura, N. ; Anand, M.B.

Author_Institution

Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

1998

fDate

9-11 June 1998

Firstpage

48

Lastpage

49

Abstract

This paper describes excellent Al filling characteristics and low resistance dual damascene interconnects obtained with a new Al reflow process using Nb liner. This novel process can fill vias of AR4 and can achieve 40-50% drop in resistance compared with current RIE-Al lines and reflow-Al lines with Ti liner. These properties are attributed to a slower reaction rate between Nb and Al. Excellent via electrical properties have been verified across 200 mm wafers using this process. This new process is a leading candidate for sub-0.25-0.15 um Al metallization.

Keywords

ULSI; VLSI; aluminium; electric resistance; integrated circuit interconnections; integrated circuit metallisation; niobium; 0.15 to 0.25 micron; AR4 vias; Al filling characteristics; Al metallization; Al reflow; Al-Nb; Nb liner; ULSI fabrication; VLSI fabrication; dual damascene interconnects; low resistance dual damascene process; reaction rate; via electrical properties; Artificial intelligence; Conductivity; Costs; Dielectrics; Electric resistance; Filling; Metallization; Niobium; Plasma measurements; Sputtering;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4770-6

Type

conf

DOI

10.1109/VLSIT.1998.689194

Filename

689194