Adjustable supply voltages and refresh cycle for process variations and temperature changing adaptation in DRAM to minimize power consumption

In this paper, we propose an approach to dynamically adjust supply voltages and refresh cycle in Dynamic Random Access Memory (DRAM). With this approach, we can save the chip power consumption with an awareness of process variations and temperature changing. While DRAM systems are generally designed for the worst case condition, they seldom operate under those scenarios. Thus, we can exploit the design slack when operating under more favorable conditions to save power. Simulations showed that it is possible to save power consumption by as much as 40%.