All digital duty-cycle correction circuit design and its applications in high-performance DRAM

Author

Feng Lin

Author_Institution

DRAM R&D, Micron Technol., Inc., Boise, ID, USA

fYear

2011

fDate

22-22 April 2011

Firstpage

1

Lastpage

4

Abstract

Duty-cycle distortion (DCD) becomes a pressing concern as the data rate in high-performance DRAM interfaces exceeds multi-gigahertz range. In order to preserve or even improve the clock duty cycle on-die across process, voltage, and temperature (PVT) corners, a duty-cycle correction (DCC) circuit is generally desired. This paper investigates a variety of DCC circuits based on different implementations. Two applications using DCC circuits are presented in detail: 1) a digital DCC for high-speed data capture, and 2) an all-digital DCC for production DDR3 DRAMs. Pros and cons for the different approaches are compared based on the simulated and silicon data.

Keywords

DRAM chips; DCC circuits; DDR3 DRAM; all-digital DCC; digital duty-cycle correction circuit design; high-performance DRAM; high-speed data capture; Clocks; Delay; Image edge detection; Random access memory; Sensitivity; Synchronization; Duty-cycle correction (DCC); clock distribution network (CDN); clock skew; data eye; delay-locked loop (DLL); duty-cycle distortion (DCD); jitter; memory interface;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electron Devices (WMED), 2011 IEEE Workshop on

Conference_Location

Boise, ID

ISSN

1947-3834

Print_ISBN

978-1-4244-9740-9

Type

conf

DOI

10.1109/WMED.2011.5767278

Filename

5767278