A novel 6.4 /spl mu/m/sup 2/ full-CMOS SRAM cell with aspect ratio of 0.63 in a high-performance 0.25 /spl mu/m-generation CMOS technology

Author

Kim, K.J. ; Youn, J.M. ; Kim, S.B. ; Kim, J.H. ; Hwang, S.H. ; Kim, K.T. ; Shin, Y.S.

Author_Institution

Samsung Electron. Co. Ltd., Yongin-City, South Korea

fYear

1998

fDate

9-11 June 1998

Firstpage

68

Lastpage

69

Abstract

A unique 6.4 μm/sup 2/ 6Tr. SRAM cell has been developed using an advanced CMOS technology implemented in 0.25 μm design rule for high density and high speed applications. Very small aspect ratio of 0.63 has been achieved for the cell design. Special features in the layout are parallel active regions and orthogonal gate electrodes, all bar shape. Stable cell operation has been obtained at 0.5 V.

Keywords

CMOS memory circuits; SRAM chips; VLSI; integrated circuit layout; integrated circuit technology; 0.25 micron; 0.5 V; CMOS SRAM cell; aspect ratio; bar shape; high density applications; high speed applications; high-performance CMOS technology; layout; orthogonal gate electrodes; parallel active regions; six transistor memory cell; stable cell operation; static RAM; CMOS technology; Delay; Electrodes; Inverters; Isolation technology; Oxidation; Parasitic capacitance; Random access memory; Shape; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4770-6

Type

conf

DOI

10.1109/VLSIT.1998.689202

Filename

689202