Title :
Buried ultra-low-energy gate implants for sub-0.25 micron CMOS technology
Author :
Bevk, J. ; Kuehne, S. ; Vaidya, H. ; Mansfield, W. ; Hobler, G. ; Boulin, D.M. ; Bolan, K. ; Chang, C.P. ; Cheung, K.P. ; Cirelli, R. ; Colonell, J.I. ; Frackoviak, J. ; Frei, M. ; Gruensfelder, C. ; Jacobson, D.C. ; Key, R.W. ; Klemens, F.P. ; Lai, W.Y.C
Author_Institution :
Bell Lab., Lucent Technol., Murray Hill, NJ, USA
Abstract :
We have demonstrated that the threshold voltage shifts in closely spaced, dual-poly CMOS devices are virtually eliminated by using buried, low energy gate implants. The reduced thermal budget for gate activation, made possible by short diffusion distances, not only reduces dopant lateral diffusion in the gates but also in the device channel regions. Moreover, the process allows the use of thinner gate oxides and shallower junctions and improves the control of L/sub eff/.
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; ion implantation; 0.25 micron; buried ultra-low-energy gate implants; device channel regions; dopant lateral diffusion reduction; dual-poly CMOS devices; gate activation; submicron CMOS technology; thermal budget reduction; threshold voltage shifts; Boron; CMOS process; CMOS technology; Fabrication; Implants; Jacobian matrices; MOS devices; Nitrogen; Space technology; Threshold voltage;
Conference_Titel :
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4770-6
DOI :
10.1109/VLSIT.1998.689205
