• DocumentCode
    3138047
  • Title

    A Testing Strategy for PLAs

  • Author

    Cha, Charles W.

  • Author_Institution
    IBM System Products Division, East Fishkill facility Hopewell Junction, NY
  • fYear
    1978
  • fDate
    19-21 June 1978
  • Firstpage
    326
  • Lastpage
    334
  • Abstract
    Programmable Logic Arrays (PLA) are finding increasing use as a cost-effective means to utilize LSI electronics. In this paper, three classes of faults, namely stuck faults, shorts and cross-point defects are defined and characterized in a PLA. The relationship between the test sets and their faults among all three classes are discussed. Finally, an algorithm for generating a test set for all three classes of faults is presented.
  • Keywords
    Circuit faults; Decoding; Driver circuits; FETs; Feeds; Large scale integration; Logic devices; Logic testing; Programmable logic arrays; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1978. 15th Conference on
  • Type

    conf

  • DOI
    10.1109/DAC.1978.1585193
  • Filename
    1585193
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3138047