Optimization of spanning tree carry lookahead adders

Author

Blackburn, Jeremy ; Arndt, L. ; Swartzlander, Earl E., Jr.

Author_Institution

Crystal Semicond. Corp., Austin, TX, USA

Volume

1

fYear

1996

fDate

3-6 Nov. 1996

Firstpage

177

Abstract

This paper examines the optimization of the 64-bit spanning tree carry lookahead adder by sizing the transistors in the different Manchester carry chain blocks and by adjusting the block widths within the carry tree to reduce the critical delay paths of the carry signals. Previous spanning tree designs are re-simulated using HSPICE, with parameters for a 0.35 /spl mu/m CMOS process, to compare against the circuits designed for this paper. After analyzing many different configurations using the 16-bit carry select boundary, two circuits employing an 8-bit carry select boundary are designed and simulated.

Keywords

CMOS logic circuits; SPICE; adders; carry logic; circuit analysis computing; circuit optimisation; critical path analysis; digital arithmetic; integrated circuit design; logic CAD; 0.35 micron; 16 bit; 16-bit carry select boundary; 64 bit; 64-bit spanning tree carry lookahead adder; 8 bit; 8-bit carry select boundary; CMOS process; HSPICE; Manchester carry chain blocks; block widths; carry signals; critical delay paths; optimization; spanning tree carry lookahead adders; transistors; Adders; Analytical models; CMOS logic circuits; CMOS process; Capacitance; Circuit simulation; Delay; Feeds; Inverters; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1996. Conference Record of the Thirtieth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-8186-7646-9

Type

conf

DOI

10.1109/ACSSC.1996.600852

Filename

600852