Title :
Carry select and input select adder for late arriving data
Author :
Schwarz, Eric M. ; McPherson, Tom ; Krygowski, Chris
Author_Institution :
IBM, Poughkeepsie, NY, USA
Abstract :
An adder is described which is optimized for the case of one of its inputs having a skewed arrival time. If the least significant bits of either of the operands arrives last, a conventional adder will not be able to execute concurrently with any of the prior computation. This paper shows a design which takes advantage of the early arriving bits and performs early computation of the sum. The adder has been fabricated and is part of the exponent unit of a future mainframe computer.
Keywords :
CMOS logic circuits; adders; circuit optimisation; integrated circuit layout; logic design; 0.25 micron; carry select adder; design; early arriving bits; early computation; fabrication; future mainframe computer component; input select adder; late arriving data; operands; skewed arrival time; Added delay; Arithmetic; Concurrent computing; Hardware; Information retrieval; Microprocessors;
Conference_Titel :
Signals, Systems and Computers, 1996. Conference Record of the Thirtieth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-8186-7646-9
DOI :
10.1109/ACSSC.1996.600853
