• DocumentCode
    3138289
  • Title

    7|2 counters and multiplication with threshold logic

  • Author

    Vassiliadis, Stamatis ; Cotofana, Sorin

  • Author_Institution
    Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
  • Volume
    1
  • fYear
    1996
  • fDate
    3-6 Nov. 1996
  • Firstpage
    192
  • Abstract
    We propose new threshold logic based, 7|2 counters. In particular we show that 7|2 counters can be implemented with threshold logic gates in three levels of gates with explicit computation of the outputs. Consequently, we improve the delay by showing that 7|2 counters can be designed with two levels of gates and implicit computation of the sum. Further we investigate multiplication schemes using such counters, in combination with Kautz´s (1961) networks for symmetric Boolean functions. Using a 32/spl times/32 direct multiplication scheme based on 7|2 implicit output computation counters and the Kautz´s networks we show that our scheme outperforms in terms of area requirements known proposals for multiplications using threshold logic.
  • Keywords
    Boolean functions; counting circuits; digital arithmetic; logic gates; threshold logic; 7|2 counters; Kautz´s networks; area requirements; delay; multiplication; symmetric Boolean functions; threshold logic gates; Counting circuits; Equations; Input variables; Logic devices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Systems and Computers, 1996. Conference Record of the Thirtieth Asilomar Conference on
  • Conference_Location
    Pacific Grove, CA, USA
  • ISSN
    1058-6393
  • Print_ISBN
    0-8186-7646-9
  • Type

    conf

  • DOI
    10.1109/ACSSC.1996.600855
  • Filename
    600855