DocumentCode
3138374
Title
Channel engineering of 0.13 /spl mu/m nMOSFET for 1.0 V CMOS using gate poly-Si oxidation and laterally profiled, surface concentrated channel technologies
Author
Momiyama, Y. ; Kurata, H. ; Ohkubo, S. ; Sugii, T.
Author_Institution
Fujitsu Lab. Ltd., Atsugi, Japan
fYear
1998
fDate
9-11 June 1998
Firstpage
78
Lastpage
79
Abstract
We have developed a 0.13 /spl mu/m nMOSFET for 1.0 V CMOS using gate poly-Si oxidation and laterally profiled surface concentrated channel technologies which realize high performance (Ion=0.47 mA//spl mu/m, Gm=680 mS/mm, Vth roll-off=33 mV) with a 74 mV/decade S-factor and a 16% reduction of Cj.
Keywords
CMOS integrated circuits; MOSFET; integrated circuit technology; low-power electronics; oxidation; 0.13 micron; 1.0 V; Si; capacitance; channel engineering; gate polysilicon oxidation; laterally profiled surface concentrated channel technology; low power CMOS IC; nMOSFET; subthreshold slope; threshold voltage roll-off; Boron; CMOS technology; Capacitance; Design engineering; Fluid flow measurement; Impurities; Insulation; Laboratories; MOSFET circuits; Oxidation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-4770-6
Type
conf
DOI
10.1109/VLSIT.1998.689207
Filename
689207
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