A Low Power Fully Programmable 1MHz Resolution 2.4GHz CMOS PLL Frequency Synthesizer

Author

Krishna, M. Vamshi ; Xie, J. ; Lim, W.M. ; Do, M.A. ; Yeo, K.S. ; Boon, C.C.

Author_Institution

Nanyang Technol. Univ., Singapore

fYear

2007

fDate

27-30 Nov. 2007

Firstpage

187

Lastpage

190

Abstract

This paper presents a low power, high resolution 2.4 GHz CMOS frequency synthesizer for low power wireless LAN applications. The PLL frequency synthesizer consists of a fully programmable frequency divider with a resolution of 1 MHz in the range of 2.4 GHz-2.484 GHz.The measured results showed that the programmable divider consumes 946 uA and Quadrature VCO consumes 1.57 mA and produces output swing of 650-700 mVpp. The complete synthesizer is designed using the Chartered RF 0.18 um process and synthesizer consumes 2.7 mA.

Keywords

CMOS integrated circuits; UHF integrated circuits; frequency dividers; frequency synthesizers; low-power electronics; phase locked loops; programmable circuits; wireless LAN; CMOS PLL frequency synthesizer; current 1.57 mA; current 2.7 mA; current 946 muA; frequency 1 MHz; frequency 2.4 GHz; fully programmable frequency divider; low power wireless LAN; quadrature VCO; voltage 650 mV to 700 mV; CMOS digital integrated circuits; Digital circuits; Energy consumption; Flip-flops; Frequency conversion; Frequency synthesizers; Phase locked loops; Radio frequency; Transceivers; Voltage-controlled oscillators; Frequency Synthesizer; Fully Programmable; high resolution; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Biomedical Circuits and Systems Conference, 2007. BIOCAS 2007. IEEE

Conference_Location

Montreal, Que.

Print_ISBN

978-1-4244-1524-3

Electronic_ISBN

978-1-4244-1525-0

Type

conf

DOI

10.1109/BIOCAS.2007.4463340

Filename

4463340