Title :
Reduction of Power Consumption in Key-specific AES Circuits
Author :
Matsuoka, Shingo ; Ichikawa, Shuichi
Author_Institution :
Dept. Mech. Syst. Eng., Asahikawa Nat. Coll. of Technol., Asahikawa, Japan
Abstract :
If any inputs of the logic circuit are fixed to constants, the circuit can be optimized by reducing the logic gates (hardware specialization). This study reports the power consumption of AES cryptographic circuit, which was specialized for a fixed encryption key. We implemented this key-specific AES circuit with a Xilinx Virtex-5 FPGA, and measured the operational frequency, the logic scale, and the power consumption. The occupied slices were reduced to 64% of that of the original, while the reduction of power consumption was limited to 3.7%.
Keywords :
circuit optimisation; cryptography; field programmable gate arrays; logic circuits; logic gates; power consumption; AES cryptographic circuit; Xilinx Virtex-5 FPGA; circuit optimization; fixed encryption key; hardware specialization; key-specific AES circuits; logic circuit; logic gates; logic scale; operational frequency; power consumption reduction; Encryption; Field programmable gate arrays; Hardware; Power demand; Read only memory; Registers; Standards; FPGA; Hardware Specialization; Partial Evaluation;
Conference_Titel :
Networking and Computing (ICNC), 2012 Third International Conference on
Conference_Location :
Okinawa
Print_ISBN :
978-1-4673-4624-5
DOI :
10.1109/ICNC.2012.61
