DocumentCode
3138985
Title
Design Space Exploration using Parameterized Cores: A Case Study
Author
Anderson, Ian D L ; Khalid, Mohammed A S
Author_Institution
Dept. of Electr. & Comput. Eng., Windsor Univ., Ont.
fYear
2006
fDate
38838
Firstpage
1893
Lastpage
1896
Abstract
Today, many designers of embedded systems are choosing to build their systems using parameterized intellectual property (IP) cores, which are hardware or software components which allow certain aspects of their architecture to be changed and set at design-time. Design space exploration (DSE) is the process of determining the best combination of parameter values from the complete set of possible designs. Designs are evaluated in terms of their objectives-usually IC chip area, power consumption and system performance. Often, automated approaches are used to prune the design space in search of the Pareto-optimal set of designs. One of the most common approaches involves using a genetic-algorithm (GA) based approach to determine this set from the complete design space. In this paper, we present the results of a case study involving the Altera Nios parameterized soft-core processor. The goal of this study is to determine the Pareto-optimal set of design configurations for the Nios processor using a genetic-based approach-the simple evolutionary algorithm for multi-objective optimization (SEAMO). From this study we conclude that genetic-based approaches can be useful in assisting designers to make intelligent choices for parameter selection
Keywords
Pareto optimisation; electronic design automation; embedded systems; genetic algorithms; integrated circuit design; IC chip design; Pareto optimal; design space exploration; embedded system; genetic algorithm; multiobjective optimization; parameterized intellectual property; simple evolutionary algorithm; Algorithm design and analysis; Computer architecture; Embedded software; Embedded system; Energy consumption; Evolutionary computation; Hardware; Intellectual property; Space exploration; System performance; Design space exploration; Pareto-optimal; embedded systems; genetic algorithms; parameterized cores;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 2006. CCECE '06. Canadian Conference on
Conference_Location
Ottawa, Ont.
Print_ISBN
1-4244-0038-4
Electronic_ISBN
1-4244-0038-4
Type
conf
DOI
10.1109/CCECE.2006.277326
Filename
4054796
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