• DocumentCode
    3139371
  • Title

    VLSI testing and test power

  • Author

    Wen, Xiaoqing

  • Author_Institution
    Dept. of Comput. Syst. & Eng., Kyushu Inst. of Technol., Iizuka, Japan
  • fYear
    2011
  • fDate
    25-28 July 2011
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    This paper first reviews the basics of VLSI testing, focusing on test generation and design for testability. Then it discusses the impact of test power in scan testing, and highlights the need for low-power VLSI testing.
  • Keywords
    VLSI; low-power VLSI testing; scan testing; test generation; test power; Circuit faults; Clocks; Delay; Integrated circuit modeling; Sequential circuits; Testing; Very large scale integration; VLSI testing; at-speed scan testing; capture power; design for testability; low-power testing; scan design; scan testing; shift power; test generation; test power;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Green Computing Conference and Workshops (IGCC), 2011 International
  • Conference_Location
    Orlando, FL
  • Print_ISBN
    978-1-4577-1222-7
  • Type

    conf

  • DOI
    10.1109/IGCC.2011.6008607
  • Filename
    6008607
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3139371