Title :
Peak power identification on power bumps during test application
Author :
Zhao, Wei ; Tehranipoor, Mohammad
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Connecticut, Storrs, CT, USA
Abstract :
Peak power during test can seriously impact circuit performance as well as the power safety for both CUT and tester. In this paper, we propose a method of layout-aware weighted switching activity identification flow that evaluates peak current/power on power bumps to detect high power patterns. The dynamic power model uses load capacitance as a metric to represent its value. Parasitic capacitance is also extracted from layout and taken into account in calculating power. Resistance network is considered regarding power bus to determine the power delivery path and power level on each specific power bump. The peak power identification flow can be integrated in gate level pattern simulation that the IR-drop results have good correlation with commercial power sign-off analysis tool.
Keywords :
CMOS integrated circuits; capacitance; integrated circuit layout; integrated circuit testing; low-power electronics; switching circuits; CMOS device; IR-drop; commercial power sign-off analysis tool; dynamic power model; layout-aware weighted switching activity identification flow; parasitic capacitance; peak power identification; power bumps; power bus; power delivery path; resistance network; test application; Capacitance; Equations; Layout; Logic gates; Mathematical model; Metals; Switches; layout partition; peak power; power bump; weighted switching;
Conference_Titel :
Green Computing Conference and Workshops (IGCC), 2011 International
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4577-1222-7
DOI :
10.1109/IGCC.2011.6008608
