A Low-Power Efficient Direct Digital Frequency Synthesizer Based on New Two-Level Lookup Table

Author

Yi, Shu-Chung ; Lee, Kun-Tse ; Chen, Jin-Jia ; Lin, Chien-Hung

Author_Institution

Graduate Inst. of Integrated Circuit Design, NCUE, Changhua

fYear

2006

fDate

38838

Firstpage

963

Lastpage

966

Abstract

This work presents a low power direct digital frequency synthesizer (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide ROM lookup table into two parts. The ROM size of the proposed architecture is 25% less than that of conventional two-level table. The hardware complexity of the new DDFS architecture compared to the traditional two-level table DDFS can be omitted one multiplier. A synthesized 0.35-mu DDFS with a SFDR of -80dB, runs up to 100MHz and consumes 81-mW at 3.0v. The power efficiency is 0.81-mW/MHz, which represents an enhancement of more than 38% compared to the conventional DDFS

Keywords

direct digital synthesis; radiocommunication; read-only storage; table lookup; direct digital frequency synthesizer; hardware complexity; trigonometric double angle formula; two-level ROM lookup table algorithm; Communication switching; Design engineering; Digital-analog conversion; Equations; Frequency conversion; Frequency synthesizers; Integrated circuit synthesis; Power engineering and energy; Read only memory; Table lookup; DDFS; Frequency Synthesizer; Low power; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2006. CCECE '06. Canadian Conference on

Conference_Location

Ottawa, Ont.

Print_ISBN

1-4244-0038-4

Electronic_ISBN

1-4244-0038-4

Type

conf

DOI

10.1109/CCECE.2006.277378

Filename

4054824