• DocumentCode
    3139577
  • Title

    A good input ordering for circuit verification based on binary decision diagrams

  • Author

    Saucier, G. ; Poirot, F.

  • Author_Institution
    Inst. Nat. Polytech. de Grenoble, France
  • fYear
    1991
  • fDate
    27-31 May 1991
  • Firstpage
    385
  • Lastpage
    387
  • Abstract
    Verification methods for standard cell logic are based on binary decision diagrams (BDD) comparison. The reference Boolean equations as well as the network of standard cell logic are represented by ordered BDDs (OBDDs). The main issue is to find a good input ordering to reduce both the number of nodes in the BDDs and the computation time needed to construct as well as to compare them.<>
  • Keywords
    Boolean functions; logic design; binary decision diagrams; circuit verification; input ordering; reference Boolean equations; standard cell logic; Binary decision diagrams; Boolean functions; Circuits; Computer networks; Construction industry; Data structures; Equations; Input variables; Logic; Minimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Euro ASIC '91
  • Conference_Location
    Paris, France
  • Print_ISBN
    0-8186-2185-0
  • Type

    conf

  • DOI
    10.1109/EUASIC.1991.212832
  • Filename
    212832
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3139577