A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories

This paper describes a self-aligned Shallow Trench Isolation (STI) process integration to realize a low cost and high reliability 1 Gbit NAND flash memory. Peripheral low voltage CMOS transistors, high voltage transistors and small 5F/sup 2/ memory cells can be fabricated at the same time by using the self-aligned STI process. The advantages are as follows. (1) The number of process steps is reduced to 60% in comparison with a conventional process. (2) a high reliability of the gate oxide is realized even for high voltage transistors because the gate electrode does not overlap the trench corner. (3) A tight distribution of the threshold voltages (2.0 V) in a 2 Mbit memory cell array is achieved due to a good uniformity of the channel width in the self-aligned STI cells. Therefore this process integration combines a low cost with a high reliability for a manufacturable 1 Gbit flash memory.