Title :
Evaluation of VLSI layout style implementations for efficiency
Author :
Robert, M. ; Trauchessec, J. ; Cathebras, G. ; Bonzom, V. ; Azemard, N. ; Deschacht, D. ; Auvergne, D.
Author_Institution :
Lab. d´´Autom. et de Microelectron. de Montpellier, CNRS, Montpellier II Univ., Sci. et Tech. Du Languedoc, France
Abstract :
As an attempt to define a priori mapping rules for performance driven layout, the authors show in this paper how an automatic module generator can be used to compare different implementation styles of regular layout. Speed and area performances of gate and linear matrix approaches are compared. It is clearly shown that abutment of diffusions results in lower ´locox´ parasitic capacitances inducing higher speed performances for linear matrix style.<>
Keywords :
VLSI; circuit layout CAD; integrated circuit technology; VLSI layout style; automatic module generator; cell compilers; gate matrix style; linear matrix style; parasitic capacitances; performance driven layout; regular layout; CMOS logic circuits; Compaction; Design automation; Integrated circuit synthesis; Integrated circuit technology; Libraries; Microelectronics; Parasitic capacitance; Silicon; Very large scale integration;
Conference_Titel :
Euro ASIC '91
Conference_Location :
Paris, France
Print_ISBN :
0-8186-2185-0
DOI :
10.1109/EUASIC.1991.212836
