Simulated evolution based code generation for programmable DSP processors

Modern DSP processors are capable of performing multiple instructions concurrently. Due to the limitation in internal structure, parallel instructions often impose constraints on the operand data types. In this paper, we propose a novel code generation method which takes both operand data type assignment and instruction scheduling problems into account. The operand data types can be adjusted during instruction scheduling to create more parallel instructions. A simulated evolution based iterative scheduling algorithm is devised to solve the operand data type assignment, instruction scheduling and register allocation problems in one. Tested benchmark programs indicate that our method can generate very efficient codes in all cases