Design of highly reliable VLSI processors incorporating concurrent error detection/correction

The full exploitation of the benefits to be gained by the high packing densities achievable by present day fabrication technologies for VLSI circuits, is overshadowed to some extent by the increase in the susceptibility of the small geometry circuits to intermittent faults. Unfortunately, standard testing strategies cannot detect these types of faults. The increased use of VLSI circuits in ´safety-critical´ applications has necessitated the incorporation of concurrent error detection/correction mechanisms into VLSI circuits to continuously monitor the operation of the circuit to detect and, in some cases subsequently correct these faults. The author describes the implementation of two schemes for concurrent error detection/correction in VLSI processors.<>