DocumentCode :
3139812
Title :
Design of highly reliable VLSI processors incorporating concurrent error detection/correction
Author :
Russell, G. ; Elliott, I.D.
Author_Institution :
Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
fYear :
1991
fDate :
27-31 May 1991
Firstpage :
316
Lastpage :
321
Abstract :
The full exploitation of the benefits to be gained by the high packing densities achievable by present day fabrication technologies for VLSI circuits, is overshadowed to some extent by the increase in the susceptibility of the small geometry circuits to intermittent faults. Unfortunately, standard testing strategies cannot detect these types of faults. The increased use of VLSI circuits in ´safety-critical´ applications has necessitated the incorporation of concurrent error detection/correction mechanisms into VLSI circuits to continuously monitor the operation of the circuit to detect and, in some cases subsequently correct these faults. The author describes the implementation of two schemes for concurrent error detection/correction in VLSI processors.<>
Keywords :
VLSI; error correction; error detection; microprocessor chips; redundancy; VLSI processors; concurrent error detection/correction; faults; monitor; small geometry circuits; Aerospace industry; Circuit faults; Circuit testing; Electrical fault detection; Error correction; Fault detection; Hardware; Monitoring; Redundancy; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Euro ASIC '91
Conference_Location :
Paris, France
Print_ISBN :
0-8186-2185-0
Type :
conf
DOI :
10.1109/EUASIC.1991.212845
Filename :
212845
Link To Document :
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