DocumentCode
3140173
Title
A genetic algorithm for the routing of VLSI circuits
Author
Geraci, M. ; Orlando, P. ; Sorbello, F. ; Vassallo, G.
Author_Institution
Centro per la Ricerca Elettronica in Sicilia, Palermo, Italy
fYear
1991
fDate
27-31 May 1991
Firstpage
218
Lastpage
223
Abstract
A channel and switch-box router based on an original and efficient optimization technique is presented. It uses modified Genetic Algorithms (GA) belonging to the family of Simulated Evolution. It combines the speed of Steepest Descent with the best features of GA, like the intrinsic high parallelism, the avoidance of local minima and an easy implementation. The algorithm can be applied both to channels and switchboxes and tests with several benchmarks have been performed; the results are qualitatively better or comparable to the most popular channel router.<>
Keywords
VLSI; circuit layout CAD; network routing; Simulated Evolution; VLSI circuits; avoidance of local minima; channel router; easy implementation; genetic algorithm; intrinsic high parallelism; optimization technique; routing; switch-box router; Algorithm design and analysis; Circuits; Design optimization; Genetic algorithms; Performance evaluation; Pins; Polynomials; Routing; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '91
Conference_Location
Paris, France
Print_ISBN
0-8186-2185-0
Type
conf
DOI
10.1109/EUASIC.1991.212864
Filename
212864
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