Title :
VLSI-oriented asynchronous controller synthesis based on a flip-flop cell array structure
Author :
Cho, K.R. ; Ikeda, M. ; Asada, K.
Author_Institution :
Dept. of Electron. Eng., Tokyo Univ., Japan
Abstract :
Presents a new implementation method of asynchronous controllers based on a cell array structure. Two kinds of cells are used to map asynchronous circuits synthesized by one-hot code assignment into layout; a basic cell with a flip-flop memory and set-reset logic, and an extension cell with set-reset logic. The present method gives considerable area reduction compared with a PLA-like implementation.<>
Keywords :
VLSI; asynchronous sequential logic; cellular arrays; flip-flops; asynchronous controller synthesis; extension cell; flip-flop cell array structure; one-hot code assignment; set-reset logic; Asynchronous circuits; Binary search trees; Central Processing Unit; Circuit synthesis; Clocks; Encoding; Flip-flops; Hardware; Logic circuits; Very large scale integration;
Conference_Titel :
Euro ASIC '91
Conference_Location :
Paris, France
Print_ISBN :
0-8186-2185-0
DOI :
10.1109/EUASIC.1991.212882
