A new approach to timing driven partitioning of combinational logic

Presents a new approach to timing driven partitioning of combinational logic. Instead of accessing a predefined library, complex gates based on the line-of-diffusion layout style are automatically synthesized. A new timing model for complex gates is presented which permits a fast pattern independent timing analysis with a deviation of less than 10% and two to three orders of magnitude faster than the exact SPICE simulation taking into account all parasitics and signal slopes. To improve the overall timing a heuristic is presented which is based on iterative partitioning techniques for complex gates. The overall performance is demonstrated on several examples.<>