Micromachined high aspect ratio coplanar waveguide with high impedance and low loss on low resistivity silicon

A micromachining process has been developed to create high impedance and low loss high aspect ratio coplanar waveguide (HARC) on low resistivity silicon. The process uses silicon DRIE to create an array of tall mesas that are spaced with a precise pitch. The silicon mesa array is then merged into a single solid SiO2 mesa using thermal oxidation. The solid SiO2 mesa creates a wide dielectric for use in high impedance HARC. The complete fabrication process includes DRIE, thermal oxidation, electroplating, planarization, and substrate removal to create HARC on low resistivity silicon with a planar surface. A high impedance HARC has been fabricated on silicon using this method. Measurements show that silicon substrate removal increases the line impedance from ∼ 20 Ohms to 57 Ohms, reduces effective dielectric constant from ∼ 6 to 2, and reduces attenuation constant from ∼ 33 dB/cm to 4 dB/cm @ 30 GHz. Measurements are compared to an analytical model derived for HARC.