DocumentCode
3140661
Title
Single-chip RNS two port parallel adaptor for wave digital filters
Author
Cardarilli, G.C. ; Sargeni, F.
Author_Institution
Dept. of Electron. Eng., Rome Univ., Italy
fYear
1991
fDate
27-31 May 1991
Firstpage
49
Lastpage
52
Abstract
A method based on the residue number system (RNS) arithmetic is used. This method allows one to overcome these difficulties and to obtain high speed and low complexity WDF devices. In particular, the speed performance can be improved through the use of parallel processors defined in terms of RNS, while the occupied area can be reduced realizing suitable isomorphism tables and reducing multiplier complexity to that of a sum. In this paper, an ASIC RNS implementation of a two-port constrained parallel adaptor for WDFs is presented.<>
Keywords
digital arithmetic; digital signal processing chips; multiport networks; parallel architectures; wave digital filters; RNS two port parallel adaptor; isomorphism tables; multiplier complexity; parallel processors; residue number system; speed performance; wave digital filters; Application specific integrated circuits; Arithmetic; Digital filters; Equations; Galois fields; Hardware; Lattices; Quantization; Very large scale integration; Zinc;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '91
Conference_Location
Paris, France
Print_ISBN
0-8186-2185-0
Type
conf
DOI
10.1109/EUASIC.1991.212895
Filename
212895
Link To Document