• DocumentCode
    3140740
  • Title

    Algorithmic ADC for use in ASIC design

  • Author

    Deevy, Kenneth

  • Author_Institution
    Analog Devices BV, Limerick, Ireland
  • fYear
    1991
  • fDate
    27-31 May 1991
  • Firstpage
    29
  • Lastpage
    33
  • Abstract
    An algorithmic analog to digital converter is described which combines a fast conversion time of less than 300 ns with a small circuit area of 0.8 mm/sup 2/. The circuit operates from a+5 V power supply and is ideally suited for use as a general purpose cell in analogue and mixed signal ASIC design. The ADC operates in current mode and an accurate current sensing technique allows the comparators to operate very quickly even in the presence of small signal differences. The current mode approach has the advantage of small signal voltage swings, low node capacitance and therefore fast operation. The resolution of the converter is 8-bits as this will satisfy the requirements of many applications including digital mobile radio and disk drive servo control chips. Results are presented for a prototype chip fabricated on a 2- mu m BiCMOS process.<>
  • Keywords
    BiCMOS integrated circuits; analogue-digital conversion; comparators (circuits); mixed analogue-digital integrated circuits; 2 micron; BiCMOS process; algorithmic analog to digital converter; circuit area; comparators; conversion time; current mode; current sensing technique; digital mobile radio; disk drive servo control; mixed signal ASIC design; node capacitance; resolution; signal differences; signal voltage swings; Algorithm design and analysis; Analog-digital conversion; Application specific integrated circuits; Capacitance; Disk drives; Land mobile radio; Low voltage; Power supplies; Signal design; Signal resolution;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Euro ASIC '91
  • Conference_Location
    Paris, France
  • Print_ISBN
    0-8186-2185-0
  • Type

    conf

  • DOI
    10.1109/EUASIC.1991.212899
  • Filename
    212899