Power Aware Scan-Based Testing using Genetic Algorithm

Power dissipation during testing is substantially higher than during normal operations due to increased switching activity. Test vector ordering is an effective method to reduce switching activity in combinational circuits and scan chain reordering has been often cited as an effective technique for reducing power dissipation in the scan chain during testing. This paper describes a technique for re-ordering of test vectors and scan cells to minimize power dissipation in full scan combinational circuits during test application. The reduction is achieved by decreasing the switching activity and spurious transitions between consequent test vectors and scan cells. We formulate the test vector and scan reordering problem as a travel salesman problem (TSP) using hamming distance between test vectors and scan cells. One of the successful approaches to solve TSP is using genetic algorithm (GA) and we use standard genetic algorithm to solve this problem. Experiments performed on the ISCAS-85 and ISCAS-89 benchmark suite show a reduction in power test applying (41% for s298) as well as a reduction in power test vector inserting (25% for s298)