An independent FPGA implementation of graphical spatial hierarchy

The customized hardware platform for spatial hierarchy construction are validly obtained Mutual channels oriented to outward manipulations are established in FPGA speedup architecture for spatial hierarchical index structures Instance parameter adjusting mechanism are scheduled and constructed in the main stem of system. Multiple facilities for process and storage are built for the presorting operations. Specialized process structures and storage structures are constructed to ensure the reutilization of presorting results on each level. The objective functions for division evaluation oriented to specific applications are scheduled. Through evaluation and concatenation for the memory accessing sequences, optimized executing strategies are generated reliably to broaden the bandwidths of accessing channels. After optimizations for algorithm and architecture, such achievement provides the starting points for future development.