A serial MAC architecture for FPGA implementation of a complex adaptive beamformer

Large scale adaptive beamformers for monopulse radars are difficult to implement on distributed FPGA arrays due to their computational complexity and/or data bandwidth requirements between FPGA processors. In monopulse target estimation, a 2D antenna array of 64 elements is employed for horizontal and vertical polarizations. For such a system sum and difference beamformers are required to estimate the target directional coordinates. In a previous communication we proposed a sparse subarray structure to reduce the computational burden. In extension to this work now we look at the problem of large amount of multipliers required for adaptive subarray systems. For eight channel fully reconfigurable subarray system, an estimated 568 multipliers are required for two polarizations. In order to reduce this requirement we propose a serial MAC architecture where four parallel multipliers are employed serially using one multiplier. In this case one fourth reduction is achieved and adaptive system can be accommodated on single FPGA device. A complex subarray adaptive beamformer is implemented using the serial MAC structure on a Xilinx device. Device occupation of the proposed adaptive system is four times better than that of parallel adaptive system.