DocumentCode
3141413
Title
Verification and Optimization for LSI & PCB Layout
Author
Brady, H. Nelson ; Smith, Robert J., II
Author_Institution
V-R Information Systems, Inc., Austin, TX
fYear
1981
fDate
29-1 June 1981
Firstpage
365
Lastpage
371
Abstract
Layout optimization involves interconnection wiring modifications, which improve aesthetic appearance, fabrication characteristics, routability, and reliability of routed boards/chips. Requirements and capabilities of a general purpose layout optimizer are presented, then organization and processing flow of the program are outlined. The functional decomposition and modular structure of this system are presented. Results achieved by using the verifier/optimizer on large printed circuit boards and gate arrays are given.
Keywords
Data mining; Data structures; Design optimization; Fabrication; Information systems; Integrated circuit interconnections; Large scale integration; Layout; Optimized production technology; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1981. 18th Conference on
Type
conf
DOI
10.1109/DAC.1981.1585383
Filename
1585383
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