Partitioning for VLSI Placement Problems

Two partition/interchange processes are described for solving VLSI placement problems. Explicit partitioning is used in both methods to decompose the initial large graph into several smaller graphs for initial placement and subsequent interchange optimization. Comparative runs were made between the two processes and against the interchange process without partitioning on problems involving a few hundred elements. The comparative results clearly establish the effectiveness of partitioning in enhancing the performance of interchange processes and constraining computation time growth. While the two methods described herein were developed for VLSI placement problems, they are applicable to quadratic assignment problems arising from numerous other settings.