Dynamic Reconfiguration for Irregular Code Using FNC-PAE Processor Cores

This paper describes PACT XPP Technologies´ Function-PAE (FNC-PAE) Processor Core which was designed for executing irregular, control-flow dominated code efficiently in embedded systems. It combines aspects of dynamically reconfigurable coarse-grain arrays and VLIW processors. The silicon-proven FNC-PAE Cores are tightly integrated with the XPP reconfigurable dataflow array. We present the FNC-PAE architecture, its development environment (assembler, C compiler, and simulator), application examples, and performance data collected from the fully working prototype chip.