Title :
A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems
Author :
Clemente, Juan Antonio ; Mozos, Daniel ; Resano, Javier
Author_Institution :
Dept. de Arquitectura de Comput. y Autom. (DACyA), Univ. Complutense de Madrid (UCM), Madrid, Spain
Abstract :
Dynamically reconfigurable hardware is a promising technology that combines in the same device both the high performance and the flexibility that many recent applications demand. However, one of its main drawbacks is the reconfiguration overhead, which involves important delays in the task execution, usually in the order of hundreds of milliseconds, as well as high energy consumption. One of the most powerful ways to tackle this problem is configuration reuse, since reusing a task does not involve any reconfiguration overhead. In this paper we propose a configuration replacement policy for reconfigurable systems that maximizes task reuse in highly dynamic environments. We have integrated this policy in an external task-graph execution manager that applies task prefetch by loading and executing the tasks as soon as possible (ASAP). However, we have also modified this ASAP technique in order to make the replacements more flexible, by taking into account the mobility of the tasks and delaying some of the reconfigurations. In addition, this replacement policy is a hybrid design-time/run-time approach, which performs the bulk of the computations at design time in order to save run-time computations. Our results illustrate that the proposed strategy outperforms other state-of- the-art replacement policies in terms of reuse rates and achieves near-optimal reconfiguration overhead reductions. In addition, by performing the bulk of the computations at design time, we reduce the execution time of the replacement technique by 10 times with respect to an equivalent purely run-time one.
Keywords :
field programmable gate arrays; logic design; reconfigurable architectures; Virtex-II Pro FPGA; configuration replacement policy; energy consumption; external task graph execution manager; hybrid design time-run time approach; near-optimal reconfiguration overhead reduction; reconfigurable hardware; task execution; task reuse; Delay; Dynamic scheduling; Field programmable gate arrays; Loading; Prefetching; Schedules; Transform coding;
Conference_Titel :
Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011 IEEE International Symposium on
Conference_Location :
Shanghai
Print_ISBN :
978-1-61284-425-1
Electronic_ISBN :
1530-2075
DOI :
10.1109/IPDPS.2011.149