Abstract :
In the last five years, there has been rapid growth in logic and memory chip circuit density. The number of different digital processors and the typical size of such processors has also grown. With all this growth, alternatives in VLSI design style as well as packaging have to be considered. These consist, on the one hand, of powerful automated placement and wiring routines, indispensable on large regular package images, and, on the other, of techniques facilitating rapid, interactive adaptation of functional logic design to the layout and interconnection of "macros" on large chips. Some results from study of each method are presented.