Using a two-dimensional fault list for compact Automatic Test Pattern Generation

Automatic Test Pattern Generation (ATPG) is one of the core algorithms in testing of digital circuits and systems. Based on a given fault model a list of all faults to be tested, i.e. the fault list, is being created. For each fault in this list, one test pattern is generated (this pattern may cover other faults). Thereby, the order of the faults is crucial. In industrial ATPG, typically a simple list is used as fault list until today. In this work, we introduce a two-dimensional fault list and different strategies to order this list. The target is to reduce the number of generated patterns. The techniques are implemented in an industrial ATPG-framework. They are evaluated on industrial circuits. The results are discussed and a general purpose strategy is given.