Analysis and Design of a 10 Gbps Transimpedance Amplifier using 0.18μm CMOS technology

Author

Bespalko, Ryan ; Frank, Brian

Author_Institution

Dept. of Electr. & Comput. Eng., Queen´´s Univ., Kingston, Ont.

fYear

2006

fDate

7-10 May 2006

Firstpage

2156

Lastpage

2159

Abstract

This paper examines the design of a 10 Gbps transimpedance amplifier (TIA) in 0.18 mum CMOS technology. In order to compensate for the high parasitic capacitances in the CMOS process, this design uses a shunt and series inductive peaking technique to achieve the required transimpedance bandwidth. A noise analysis on the input stage of the TIA is shown. This noise model is used to determine the optimum device size required to minimize the average input referred noise current. Simulation results for the TIA are presented showing a transimpedance gain of approximately 52 dBΩ. The simulated average input referred noise current of the differential TIA is shown to be approximately 27 pA/√radicHz

Keywords

CMOS integrated circuits; differential amplifiers; 0.18 micron; 10 Gbits/s; CMOS technology; TIA; noise analysis; series inductive peaking technique; shunt inductive peaking technique; transimpedance amplifier; Bandwidth; CMOS process; CMOS technology; Circuit noise; Feedback; Optical amplifiers; Optical noise; Parasitic capacitance; Resistors; Shunt (electrical); CMOS; Noise Analysis; Optical communications; Transimpedance Amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2006. CCECE '06. Canadian Conference on

Conference_Location

Ottawa, Ont.

Print_ISBN

1-4244-0038-4

Electronic_ISBN

1-4244-0038-4

Type

conf

DOI

10.1109/CCECE.2006.277643

Filename

4054960