32 bits Comparator for Multi-number Systems

One design method of 32 bits comparator for multi-number systems was proposed. In this method, 64 bits double precision floating point data and 32 bits single precision floating point data based on IEEE754 standard, 32 bits signed fixed point data and 32 bits unsigned fixed point data can be processed by the same comparator. An RTL module was implemented based on the proposed method. This RTL module was composed by 8 sub-units: control unit, extension unit, 1 bit signed compare unit, 32 bits unsigned compare unit, priority arbiter1, priority arbiter2, pipeline register and initial condition generator. All units were designed in register translation level in VHDL. EP2C5Q208C7 is the target device of implementation. The resource utilization and maximum frequency of this module were estimated. The simulation results were discussed. The correctness and quality of this method can be confirmed by simulation results.