Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs

Module-based partial reconfiguration of FPGAs offers great possibilities for runtime flexibility. It enables hardware tasks to swap in and out the design without interruption of the entire system. In this context the techniques of module relocation and the 2-dimensional reconfiguration have been successfully applied in order to reduce the storage requirement for partial bit-streams and to shorten the reconfiguration times significantly. Besides the adaptation on functional level, multiple clock domains and dynamic frequency scaling are key techniques to achieve an adaptation on power and performance level as well. However, current approaches of module relocation provide no support for designs with multiple clock domains. In this paper we present a new method of online clock network routing, which solves this problem. The concept is based on a "on the fly" manipulation of configuration bits which determine the clk-inputs of the single slices. The method is implemented in hardware in order to maximize configuration performance. Our results show that a memory saving of 66% for an example design can be achieved while the original reconfiguration speed could be maintained. Figures for hardware usage are also given.