A 27 GHZ Phase-Lock Loop Phase Detector

This paper will present an investigation into the phase detector of a 27 GHz phase-lock loop (PLL) clock multiplier using a 0.18 - mum CMOS process. The phase detector is one part of a multi-faceted project involving the development and verification of the various components composing the phase-lock loop. A low multiplication factor has been selected that provides a benefit in the multiplicative phase noise contribution, requiring a high-speed frequency divider and phase detector. The challenges of developing stable, low-jitter clock sources become greater as the operating frequency is increased. With the integration of digital and analog circuits CMOS technologies are a preferred solution because of their documented high-frequency performance and well-established manufacturing base. A study of the non-ideal performance (i.e., non-90deg phase offset for a 0 V control voltage output in the phase detector) has been undertaken; the offset may be lessened with an increase in the local oscillator switching core gate-source voltage. Simulated and measured results for a Gilbert cell phase detector realized in the TSMC 0.18-mum CMOS process and operating at 6.75 GHz are presented