DocumentCode :
3142816
Title :
Execution time reduction of Differential Power Analysis experiments
Author :
Di Natale, Giorgio ; Flottes, Marie-Lise ; Rouzeyre, Bruno
Author_Institution :
Lab. d´´Inf., Univ. Montpellier II, Montpellier
fYear :
2009
fDate :
2-5 March 2009
Firstpage :
1
Lastpage :
5
Abstract :
Cryptographic devices can be subject to side-channel attacks that consist in retrieving secret data by observing physical properties of the device. Among those attacks, differential power analysis (DPA) has proven to be very effective and easy to perform. Several countermeasures have been proposed in the literature and one of the most promising is based on power balanced design. There are still not known methods for manufacturing test of power balanced circuits, aside from performing full DPA. This paper proposes a novel method that allows to drastically reduce the number of input vectors used for the DPA, thus reducing the overall test time.
Keywords :
cryptography; cryptographic devices; differential power analysis; secret data; side-channel attacks; Circuit faults; Circuit testing; Cryptography; Data security; Energy consumption; Information retrieval; Logic design; Logic devices; Performance evaluation; Protection;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Workshop, 2009. LATW '09. 10th Latin American
Conference_Location :
Buzios, Rio de Janeiro
Print_ISBN :
978-1-4244-4207-2
Electronic_ISBN :
978-1-4244-4206-5
Type :
conf
DOI :
10.1109/LATW.2009.4813819
Filename :
4813819
Link To Document :
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