The approach to multiple instruction execution in the GMICRO/400 processor

This paper describes the instruction execution mechanism of the 32-bit microprocessor GMICRO/400 that executes more than one operation per clock cycle. The chip integrates a dual operation integer unit, a floating-point unit, an 8-Kbyte instruction cache, an 8-Kbyte data cache, and a 64-bit external data bus. The GMICRO/400 utilizes both superscalar and VLIW design techniques. The integer unit and the floating-point unit concurrently execute two integer and one floating-point instructions. The dual operation integer unit executes two operations in one clock cycle, under the control of a microprogram using long microinstruction words, when it executes a multiple-operation instruction