Optimization of a 0.18 /spl mu/m 1.5 V CMOS technology to achieve 15 ps gate delay

Author

Yang, I.Y. ; Gilbert, P. ; Pettinato, C. ; Anderson, S.G.H. ; Woodruff, R. ; Misra, V. ; Bhat, N. ; Reid, K. ; Lii, T. ; Yuan, C. ; Dyer, D. ; O´Meara, D. ; Collins, S. ; De, H. ; Veeraraghavan, S.

Author_Institution

Network Comput. & Syst. Group, Motorola Inc., USA

fYear

1998

fDate

9-11 June 1998

Firstpage

148

Lastpage

149

Abstract

A high performance 0.18 μm CMOS technology with minimum 0.1 and nominal 0.13 μm poly gate, physical 3 nm gate oxide, and 0.18 μm local interconnect features operating at 1.5 V supply voltage is described with emphasis on the reduction of parasitic capacitances and resistances while maintaining high drive currents and low leakage currents to achieve a 15 ps unloaded ring oscillator delay. Coupling capacitance between gate and local interconnect is also discussed as a function of technology scaling as is 3 nm gate oxide reliability.

Keywords

CMOS digital integrated circuits; VLSI; capacitance; delays; integrated circuit manufacture; integrated circuit technology; leakage currents; 0.18 micron; 1.5 V; 15 ps; 3 nm; CMOS technology optimisation; coupling capacitance; gate oxide reliability; high drive currents; local interconnect; low leakage currents; parasitic capacitance reduction; parasitic resistance reduction; polysilicon gate; CMOS technology; Computer networks; Delay; Doping; High performance computing; Implants; Leakage current; MOS devices; Parasitic capacitance; Rapid thermal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4770-6

Type

conf

DOI

10.1109/VLSIT.1998.689235

Filename

689235