Three-Phase PLL Synchronization with Gated Error Control

Utility powered applications often require some means of synchronization with the line voltage for the operation of the controller. Such synchronization is typically accomplished using a phase-locked loop (PLL) mechanism, which aims to estimate the phase angle of the line voltage in real time. This phase estimate then serves as a basis for signal timing for power control devices. Common phase detection methods using multipliers or zero-crossing detection require subsequent low-pass filtering for averaging purposes, resulting in longer system response, and increases in transient losses. A method is proposed for 3-phase systems which directly subtracts respective normalized line phase signals from locally synthesized 3-phase signals for instantaneous phase error estimation. The phase-locked oscillator internally defines six intervals per period, and operates a multiplexer to select the proper error signal for each interval, resulting in a faster, continuous, estimate of the phase error signal with which to drive the local oscillator toward synchronization. Simulation results are presented t o validate the proposed mechanism